1. Field of the Invention
The present invention relates to a memory control system for use in a microcomputer, and more specifically to a memory control system for a memory address management in a microcomputer.
2. Description of Related Art
Recently, application fields of microcomputers are more and more increasing so as to cover office automation instruments such as a printer and a facsimile and other instruments and apparatuses. Function and performance of these instruments have remarkably increased, and correspondingly, a program for a so called system control has been increased, and the amount of required data processing has also become voluminous. In addition, the capacity of the memory consumed in the system continues to increase.
Furthermore, various type memory devices have been required in accordance with their use purposes. For example, a non-volatile memory such as a ROM (read only memory) and a PROM (programmable ROM) is used for storing a fixed data such as a program and graphic information for character fonts, and a volatile memory such a static RAM (random access memory) and a dynamic RAM is used for storing temporary processing data such as program variables.
Under the above mentioned circumstance, as one means for increasing the performance of the system, them is a memory management system for efficiently utilizing various large-scaled memories, and various memory control systems have been known.
In one typical conventional memory control system, a memory of a microcomputer is managed by dividing the memory space into a plurality of memory areas having a relative small memory capacity, which is called a bank. For example, a full memory space of 1M byte (M:Mega=2.sup.20) is partitioned into 16 banks ("BANK 0" to "BANK 16") each of which is composed of 64K byte (K:Kilo=2.sup.10). A wait cycle can be inserted into a memory access cycle performed for each of the banks, and the number of waits can be designated for each of the banks.
Here, the designation of the wait number is performed by setting a predetermined data into a designation register. For example, a wait number designation bit of three bits is assigned in the designation register. If "0, 0, 1" is set, a wait cycle of one state is inserted, and if "0, 1, 0" is set, a wait cycle of two states is inserted. If "1, 1, 1" is set, a wait cycle of maximum seven states can be inserted.
Generally, if the wait cycle is inserted in an ordinary memory access cycle, it results in drop of performance of the overall system. For example, if the wait cycle of one state is inserted into the memory access cycle which should ordinarily be completed with three states, the performance drop of about 33% occurs each time one memory access time concerned is generated.
On the other hand, in order to avoid insertion of the wait cycle, it is necessary to use a high speed memory device, and correspondingly, the overall system becomes expensive. Therefore, it is necessary to insert a minimum number of wait cycles in consideration of the cost performance of the system and the memory structure, and it is also necessary to independently designate the wait number for each of the banks, in order to be able to comply with various system constructions.
For this purpose, a first designation register is allocated for "BANK 0", and similarly, second to sixteenth designation registers are allocated for "BANK 1" to "BANK 15, respectively. In addition, the respective designation registers are set in the course of execution of an initializing routine of the program, so that a predetermined number of wait cycles is automatically inserted in the memory access to each of the banks.
On the other hand, assume that a mask ROM for the program is assigned to "BANK 0", a static RAM for program variables is assigned to "BANK 1" and "BANK 2", and a dynamic RAM for processing data is assigned to "BANK 3" to "BANK 15". In this case, for example, "0, 0, 1" is set in the first designation register, and "0, 0, 0" is set in the second and third designation registers. Further, "0, 1, 1" is set in the fourth to sixteenth designation registers. With this, when the mask ROM is accessed, the wait cycle of one state is automatically inserted, and when the dynamic RAM is accessed, the wait cycle of three states is automatically inserted. On the other hand, when the static RAM is accessed, no wait cycle is inserted. Thus, the system is constructed such that, dependent upon the access time of the memory device to be accessed, an optimum number of wait cycles are inserted into the access cycle to the bank for which the memory device to be accessed is mapped
In the conventional memory management system as mentioned above, however, one designation register is required for each one of the hanks, and therefore, 16 designation registers are required for "BANK 0" to BANK 15" in the above mentioned example.
In addition, from the viewpoint of the program design, the same kind of memories are mapped to be continuous to each other. Therefore, it is necessary to set the same wait number into a plurality of designation registers corresponding to a corresponding number of banks of the same kind of memories used in the system. This lowers the efficiency of the program execution.